1. Technical Field
The present invention relates to methods for tuning (i.e., trimming) resistors of a chip, and more particularly, to a method for tuning resistors of a chip that can be used both before and after chip packaging.
2. Related Art
Conventional manufacturing controls on processes for forming passive devices, such as resistors in CMOS (Complementary Metal Oxide Silicon) chips, fall short of current circuit design requirements. Current industry standard I/O (Input/Output) specifications are exceeding what can be achieved in current manufacturing processes. Within analog and RF (radio frequency) semiconductors, the need for tuning the electrical resistance values of the resistors on an integrated circuit to a specific nominal value is growing to meet complex design specification requirements. Manufacturing excess chips and then sorting for required parameters is one solution, but this is a costly and not consistent with manufacturing techniques. Laser ablation is used to trim in the manufacture of some precision passive devices, but this process is inconsistent with the CMOS/BiCMOS or Analog process flow as a measurement and feedback loop is required as well as individual laser trimming of a multitude of devices on a single chip. A third known solution is to design active controls into the circuitry to compensate for manufacturing variability, but this takes up space, increases complexity, and can lead to trade-offs in performance.
Therefore, there is a need for a novel resistance structure that can be tuned to a specification. Also, there is a need for a method for tuning the novel resistance structure.